1. Field of the Invention
The present invention relates to a leadless chip resistor capacitor carrier (LCRCC) which is surface mountable to a printed circuit board. When populated with integrated circuits (ICs), the LCRCC provides a package for the ICs on the LCRCC.
2. Description of the Prior Art
Hybrid circuits are known in the prior art. A hybrid circuit typically includes a plurality of integrated circuits (ICs) mounted onto a hybrid board.
Prior to mounting the ICs onto the hybrid board, the ICs are first placed on a printed alumina substrate and wire bonded there to. The alumina substrate is then placed in a carrier and packaged. The carriers used to package the ICs include leaded chip carriers and leadless chip carriers. The ICs may also be packaged in a "TapePak" carrier. "TapePak" is a registered trademark of National Semiconductor Corporation, and is described in U.S. Pat. Nos. 4,701,781 and 4,801,561 assigned to the assignee of the present invention. Once the ICs are packaged, the carriers are ready to be mounted onto the hybrid board.
Referring to FIG. 1, a typical leaded chip carrier according to the prior art is shown. The leaded chip carrier 24 includes an alumina substrate 25 with a metallization interconnect and passive elements formed thereon, a thermally conductive pad 26, a plurality of leads 27, a ring 28 to hold the leads in position, and a cover 29. One or more ICs are mounted onto the alumina substrate 25 and wire bonds are formed between the ICs and the interconnect. The alumina substrate is then mounted onto the thermally conductive pad 26 and wire bonds are formed between the interconnect on the alumina substrate and the leads 27 of the carrier. The cover is then sealed over the carrier to complete the packaging of the IC in the carrier.
Referring to FIG. 2, a leadless chip carrier according to the prior art is shown. The leadless chip carrier 30 is identical to the leaded chip carrier 24, except the plurality of leads 27 are replaced by a plurality of conductive lines 32 which are held in position by the carrier 30. A plurality of contact regions 38 are arranged around the periphery of the carrier 30. Each of the surface contact regions 38 is coupled to one of the conductive lines 36. One or more ICs are mounted onto the alumina substrate 25 and wire bonds are formed between the ICs and the interconnect. The alumina substrate is then mounted onto the thermally conductive pad 26 and wire bonds are formed between the interconnect on the alumina substrate and the conductive lines 36 of the carrier. The cover is then sealed over the carrier to complete the packaging of the IC in the carrier.
A number of drawbacks are associated with the prior art carriers. First, an alumina substrate is required for mounting the ICs. Second, a separate leaded or leadless carrier is required to package and cover the ICs on the alumina substrate. Third, once the carrier is covered and mounted onto either a hybrid circuit or a PC board, the passive devices formed on the alumina substrate cannot be trimmed. The consequences of these problems are discussed in detail below.
Alumina substrates are made using a number of manufacturing techniques, including thick film, thin film or a green tape process. Which ever technique is used, a series of masking, printing and firing steps is required to selectively pattern the conductive areas of the interconnect and the passive elements onto the top surface of the alumina substrate.
Leaded, leadless and "TapePak" carriers are expensive and difficult to manufacture. For plastic carriers, a customized injection mold is required to form the carrier and the cover. For ICs which need to be hermetically sealed, a custom fitted ceramic carrier and cover are required. Whether a plastic or ceramic carrier is used, substantial tooling, equipment and capital is required to produce the leaded and leadless chip carriers. In addition, the substrate of the hybrid must also be manufactured. Accordingly, the carriers and substrate represent a significant percentage of the overall cost of a hybrid.
The material used to form the carriers, whether plastic or ceramic, is usually different than the alumina used to form the substrate of the hybrid. Thus during hybrid operation, the carrier may become heated, resulting in a thermal mismatch between the carrier and the substrate of the hybrid.
After mounting the carrier onto either a hybrid circuit or a PC board, the passive elements on the alumina substrate can not be actively trimmed. Without the ability to trim, the output parameters of the ICs within the carrier cannot be matched with those of other electrical devices on the hybrid circuit or PC board. As a result, the integrity and speed of the data transmitted between the IC(s) in the carrier and other devices on the hybrid circuit or the PC board may be less than ideal.
If a significant mismatch exists between an IC in the carrier and these other devices, a re-design of of the ICs may be required. Re-design is an expensive task, requiring significant engineering effort to change the circuit design, layout and/or mask set for the IC. In addition, the re-design will often take months to complete, which can significantly reduce the market opportunity of a semiconductor manufacturer.